"Traditional HLS methodologies continue to incur significant hardware engineering resources to translate my algorithms to RTL for implementation into FPGA or ASIC silicon. "The Synphony HLS solution will dramatically change how FPGAs and ASICs are used for system validation and embedded software development," said Richard Cagley, Ph.D., algorithm developer, Toyon Research Corporation.
Cadence synopsys verification#
Unified verification across multiple flows including prototyping and ASIC implementation.C-model generation for early software development and fast system validation.Rapid prototyping methodology for early algorithm validation.Synthesis of optimized RTL architectures for ASIC and FPGA.An automated flow from M to optimized RTL.The Synphony HLS solution delivers significantly higher productivity than traditional methods by providing benefits such as: Synphony HLS integrates with Synopsys' Design Compiler®, Synplify® Premier, Confirma™, VCS®, System Studio and Innovator products to deliver the most comprehensive prototyping, implementation and verification flows from algorithm to silicon. In addition, Synphony HLS complements C/C++-based flows by generating C-models for system validation and early software development in virtual platforms. Synphony HLS creates optimized RTL for ASIC and FPGA implementation, architecture exploration and rapid prototyping.
(NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today introduced its Synphony HLS (High Level Synthesis) solution that integrates M-language and model-based synthesis to deliver up to 10X higher design and verification productivity than traditional RTL flows for communications and multimedia applications. 12 / PRNewswire-FirstCall/ - Synopsys, Inc.